1. Field of the Invention
This invention relates to a successive approximation analog-to-digital converter (ADC) (a.k.a., a SAR ADC), especially to a test method and a test circuit for the successive approximation ADC.
2. Description of Related Art
FIG. 1 illustrates a functional block diagram of a conventional charge redistribution successive approximation analog-to-digital converter (SAR ADC). In an operation period of the SAR ADC, the successive approximation register (SAR) 120 decides, according to the clock signal, one of the bit values (I/O) of a digital output code Dn based on a comparison result of the comparator 105. The control circuit 130 generates the control signal Csw according to the digital output code Dn. The digital-to-analog converter (DAC) 110 adjusts the switching state of the capacitor array provided therein according to the control signal Csw (e.g., controlling one end of a capacitor to be connected to ground or a reference voltage Vref). As a result, the charges on the capacitors redistribute, causing the voltage levels at the inverting input terminal and the non-inverting input terminal of the comparator 105 to change, and therefore one of the voltage levels to be compared in the next operation period of the SAR ADC is changed. By repeating the above procedures, the value represented by the digital output code Dn approaches the amplitude of the input signal Vi as the digital output code Dn is decided in an order from the most significant bit (MSB) to the least significant bit (LSB).
A differential nonlinear (DNL) error of the SAR ADC is often observed in determining whether the SAR ADC meets the design criteria. This approach, however, needs to collect a large amount of DNL errors; for example, a 12-bit SAR ADC needs 40960 sets of data (10 sets of data being collected for each digital value), and all the data needs to be processed by digital signal processing (DSP) before it can be analyzed to obtain the characteristics of the DNL errors. Such huge amount of data and the DSP operation render the testing inefficient.